In general, integrated circuit testers excite one or more pins of a device under test (DUT), and then wait for the response of the DUT. In order to qualify the response, a response unit detects the state of the DUT's output signal at certain points in time, and/or triggers on state changes occurring during a prescribed time window.
The latter function, i.e. the detection of state changes of an unknown binary signal during predefined time intervals, is already addressed in DE-C-33 46 942. The circuit described in this document uses two D flip-flops for the comparison.
Another, more sophisticated approach is disclosed in EP-B-325 670. Two edge triggered D flip-flops are alternatingly activated by two pulse sequences. The D input of either flip-flop is connected with the output of respective a OR gate, wherein the Q outputs of the flip-flops are fed back to one input of the respective OR gate. The feedback loops thus lock the respective flip-flop as soon as a transition of the unknown binary signal occurs during a prescribed time window.
Both prior art approaches use D flip-flops as major components of the detector circuit. However, the use of D flip-flops implies considerable recovery times in the circuit. The required recovery times, in turn, limit the applicability of the detector circuit in two respects:
1. An interfering or disturbing pulse of short pulse width cannot be detected. This is because the recovery time of the flip-flop is longer than the duration of the disturbing pulse, such that the feedback loop cannot cause the flip-flop to lock. The prior art design thus limits the detectable pulse width of disturbing pulses. PA1 2. The required recovery time forces a modest repetition rate of the predefined control windows, which, in turn, leads to moderate test frequencies and long test cycles. PA1 1. at least one comparator circuit receiving the unknown binary signal, PA1 2. a 1-of-n decoder coupled to the output of the comparator circuit, and PA1 3. at least one latch circuit connected with at least one output of said 1-of-n decoder, wherein the latch circuit comprises a feedback loop which may be activated by a control signal. PA1 a first gate, PA1 a second gate, PA1 2. feeding an output signal of the comparator circuit to an input of a 1-of-n decoder, and PA1 3. feeding the output signal of the 1-of-n decoder to a latch circuit comprising a feedback loop which may be activated by a control signal.
The above effects restrict the applicability of the prior art circuits for integrated circuits with complex functionality like new microprocessors, RISC (reduced instruction set) CPU's and their peripheral IC's.